1
GATE EE 2002
Subjective
+5
-0
Obtain a state variable representation of the system governed by the differential equation: $${{{d^2}y} \over {d{t^2}}} + {{dy} \over {dt}} - 2y = u\left( t \right){e^{ - t}},\,\,\,$$ with the choice of state variables as $${x_1} = y,$$ $${x_2} = \left( {{{dy} \over {dt}} - y} \right){e^t}.$$ Aso find $${x_2}\left( t \right),$$ given that $$u(t)$$ is a unit step function and $${x_2}\left( 0 \right) = 0.$$
2
GATE EE 2002
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown in Fig. the Boolean expression for the output $$Y$$ in terms of inputs $$P,$$ $$Q,$$ $$R$$ and $$S$$ is GATE EE 2002 Digital Electronics - Logic Gates Question 6 English
A
$$\overline P + \overline Q + \overline R + \overline S $$
B
$$P+Q+R+S$$
C
$$\left( {\overline P + \overline Q } \right)\left( {\overline R + \overline S } \right)$$
D
$$(P+Q) (R+S)$$
3
GATE EE 2002
MCQ (Single Correct Answer)
+1
-0.3
The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is GATE EE 2002 Digital Electronics - Sequential Circuits Question 23 English
A
$$10$$ $$kHz$$
B
$$2.5$$ $$kHz$$
C
$$20$$ $$kHz$$
D
$$5$$ $$kHz$$
4
GATE EE 2002
Subjective
+5
-0
The ripple counter shown in Fig. is made up negative edge triggered $$J$$-$$E$$ flips flops. The signal levels at $$J$$ and $$K$$ inputs of all the flip-flops are maintained at logic $$1$$. Assume that all outputs are cleared just prior to applying the clock signal. GATE EE 2002 Digital Electronics - Sequential Circuits Question 6 English

$$(a)$$ Create a table of $${Q_0},{Q_1},{Q_2}$$ and $$A$$ in the format given below for $$10$$ successive
$$\,\,\,\,\,\,\,\,$$ input cycles of the clock $$CLK1.$$
$$(b)$$ Determine the module number of the counter.
$$(c)$$ Modify the circuit of Fig. to create a modulo$$-6$$ counter using the same
$$\,\,\,\,\,\,\,$$ components used in the figure.

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