The ripple counter shown in Fig. is made up negative edge triggered $$J$$-$$E$$ flips flops. The signal levels at $$J$$ and $$K$$ inputs of all the flip-flops are maintained at logic $$1$$. Assume that all outputs are cleared just prior to applying the clock signal.

$$(a)$$ Create a table of $${Q_0},{Q_1},{Q_2}$$ and $$A$$ in the format given below for $$10$$ successive
$$\,\,\,\,\,\,\,\,$$ input cycles of the clock $$CLK1.$$
$$(b)$$ Determine the module number of the counter.
$$(c)$$ Modify the circuit of Fig. to create a modulo$$-6$$ counter using the same
$$\,\,\,\,\,\,\,$$ components used in the figure.

The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal available at $$Q$$ is

For the circuit shown in Fig. the Boolean expression for the output $$Y$$ in terms of inputs $$P,$$ $$Q,$$ $$R$$ and $$S$$ is

An electrical network is fed by two $$ac$$ sources, as shown in Fig. Given that
$${Z_1} = \left( {1 - j} \right)\Omega ,\,\,{Z_2} = \left( {1 + j} \right)\Omega $$ and $${Z_L} = \left( {1 + j0} \right)\Omega .$$ Obtain the Thevenin equivalent circuit (Thevenin voltage and impedance) across terminals $$X$$ and $$Y$$, and determine the current $${{\rm I}_L}$$ through the load $${Z_L}.$$