1
GATE ECE 2026
Numerical
+1
-0.33

The negative edge triggered $J K$ flip-flop in the Figure has $J$ and $K$ inputs tied to Logic High and a square wave of 10 cycles/second is applied to its clock $(C)$ input. The frequency of the output $Q$ (in cycles/second) is $\_\_\_\_$ .

(rounded off to two decimal places)

GATE ECE 2026 Digital Circuits - Sequential Circuits Question 2 English

Your input ____
2
GATE ECE 2026
MCQ (Single Correct Answer)
+2
-0.67

What is the 10 's complement of $(47)_{10}$ ?

A

52

B

53

C

54

D

55

3
GATE ECE 2026
MCQ (Single Correct Answer)
+2
-0.67

A Boolean function, $f(x, y, z)$ with $x$ as MSB and $z$ as LSB is realized by $4: 1$ multiplexer (MUX) with select lines, $S_1$ and $S_0$ ( $S_1$ is MSB, $S_0$ is LSB) and inputs, $I_0, I_1, I_2, I_3$ as shown in the Figure.

Which of the following options is the correct expression of $f(x, y, z)$ ?

GATE ECE 2026 Digital Circuits - Combinational Circuits Question 1 English
A

$x z+y$

B

$x \bar{y}+z$

C

$x y+\bar{z}$

D

$\bar{x} y+\bar{z}$

4
GATE ECE 2026
MCQ (Single Correct Answer)
+2
-0.67

A shift-left Shift Register (SR) and a $D$ flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay.

Which of the following options gives the correct binary representation $\left(b_7 b_6 b_5 b_4 b_3 b_2 b_1 b_0\right)$ of the content of the shift register immediately after the $5^{\text {th }}$ clock transition (positive edge)?

GATE ECE 2026 Digital Circuits - Sequential Circuits Question 1 English

A

00011111

B

10111111

C

00111111

D

11000011