If X=1 in the logic equation $$\left[ {X + Z\left\{ {\overline Y + (\overline Z + X\overline {Y)} } \right\}} \right]$$ $$\left\{ {\overline X + \overline Z (X + Y)} \right\} = 1,$$ then

What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate?

The full forms of the abbreviations TTL and COMS in reference to logic families are

What are the counting states (Q₁, Q₂) for the counter shown in the figure below?