A pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is ______ n sec.

2’s complement representation of a 16-bit number (one sign bit and 15 magnitude bits) is FFFI. Its magnitude in decimal representation is

Boolean expression for the output of XNOR (equivalence) logic gate with inputs A and B is

For the logic circuit shown in Figure, the output is equal to