A 2-input up/down synchrconous counter using two toggle flip-flops is shown in Fig.1. The counter's sequence is to be controlled by the input M as follows:
For M=1, sequence of Q₁, Q₀ is ..00, 01, 10, 11, 00, 01.......
For M=0, sequence of Q₁, Q₀ is ..00, 11, 10, 01, 00, 11......

(a)Design the necessary feedback logic for T₁ and T₀.

(b)Realize the feesback logic using inverters and 4-input multiplexers only. Use Q₁ and Q₀ as the control inputs of the multiplexer with Q₁ as the MSB.

The circuit diagram of a 2 bit A to D converter is shown in figure below. The combinational logic is to be disigned to provide a natural binary representation using $${D_1}$$ and $${D_0}$$ for the analog input $${V_i}$$. $${D_1}$$ is to be the most significant bit.
(a) Draw the Karnaugh maps for $${D_1}$$ and $${D_0}$$ in terms of $${C_2}$$, $${C_1}$$ and $${C_0}$$
(b) Obtain the minimal sum of products expressions for $${D_1}$$ and $${D_0}$$.
(c) Realize the logic for $${D_1}$$ and $${D_0}$$ using 2- input NAND gates only.
(d) Find the resolution of the Ato D converter.

Given that for a logic family,

$${V_{OH}}$$ is the minimum output high-level voltage
$${V_{OL}}$$ is the minimum output low-level voltage
$${V_{IH}}$$ is the minimum output high-level voltage and
$${V_{IL}}$$ is the minimum output low-level voltage.
The correct relationship is:

Fill in the blanks of the statements below concerning the following Logic Families:
Standard TTL (74XX), Low power TTL(74LXX) Low power schottky TTL(74LSXX), schottky TTL(74 SXXX), Emitter coupled Logic (ECL), CMOS

(a) Among the TTL Families, ________ family requires considerably less power than the standard TTL (74XX) and also has com parable proparation delay.
(b) Only the _______ family can operate over a wide range of power supply voltages.