An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from 0 V to 7.68 V . If the digital input code is 10010110 (the leftmost bit is MSB). Then the analog output voltage of the DAC (rounded off to one decimal place) is

$\_\_\_\_$ V.

The propagation delay of the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns . The propagation delay of all the flip-flops is assumed to be Zero. The clock (Clk) frequency provided to the circuit is 500 MHz .

Starting from the initial value of the flip-flop outputs $Q_2 Q_1 Q_0=111$ with $D_2=1$, the minimum number of triggering clock edges after which the flip-flop outputs $Q_2 Q_1 Q_0$ becomes 100 (in integer) is $\_\_\_\_$

Consider a rectangular coordinate system $(x, y, z)$ with unit vectors $a_x, a_y$ and $a_z$. A plane wave traveling in the region $z \geq 0$ with electric field vector $E=10 \cos \left(2 \times 10^8 t+\beta z\right) a_y$ is incident normally on the plane at $z=0$, where $\beta$ is the phase constant. The region $z \geq 0$ is in free space and the region $z<0$ is filled with a lossless medium (permittivity $\varepsilon=\varepsilon_0$ permeability $\mu=4 \mu_0$, where $\varepsilon_0=8.85 \times 10^{-12} \mathrm{F} / \mathrm{m}$ and $\mu_0=4 \pi \times 10^{-7} \mathrm{H} / \mathrm{m}$ ). The value of the reflection coefficient is

The impedance matching Network shown in figure is to match a lossless line having characteristic impedance $Z_o= 50 \Omega$ with a load impedance $Z_L$. A quarter - Wave line having a characteristic impedance $Z_1=75 \Omega$ is connected to $Z_L$. Two stubs having characteristic impedance of $75 \Omega$ each are connected to this quarter - wave line. One is a short - circuited (S.C) stub of length $0.25 \lambda$ connected across PQ and the other one in an open - Circuted (O.C) stub of length 0.5 $\lambda$ connected across RS.

The impedance matching is achieved when the real part of $Z_L$ is