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## Marks 1

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Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address sp...
GATE CSE 2022
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a wri...
GATE CSE 2022
Consider a set-associative cache of size 2 KB (1 KB = 210 bytes) with cache block size of 64 bytes. Assume that the cach...
GATE CSE 2021 Set 2
A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate o...
GATE CSE 2020
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main...
GATE CSE 2019
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system ha...
GATE CSE 2019
A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$...
GATE CSE 2018
A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two b...
GATE CSE 2016 Set 1
Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct ma...
GATE CSE 2015 Set 3
Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a ...
GATE CSE 2015 Set 2
An access sequence of cache block addresses is of length $$N$$ and contains $$n$$ unique block address. The number of un...
GATE CSE 2014 Set 1
In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The l...
GATE CSE 2013
The amount of $$ROM$$ needed to implement a $$4$$ bit multiplier is
GATE CSE 2012
A main memory unit with a capacity of $$4$$ megabytes is built using $$1M \times 1$$-bit $$DRAM$$ chips. Each $$DRAM$$ c...
GATE CSE 2010
How many $$32k$$ x $$1$$ $$RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?
GATE CSE 2009
Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ gen...
GATE CSE 2007
Increasing the $$RAM$$ of a computer typically improves performance because
GATE CSE 2005
More than one word are put in one cache block to
GATE CSE 2001
The main memory of a computer has $$2$$ $$cm$$ blocks while the cache has $$2$$ $$c$$ blocks. If the cache uses the set ...
GATE CSE 1999
A $$ROM$$ is used to store the table for multiplication of two $$8$$ bit unsigned integers. The size of $$ROM$$ required...
GATE CSE 1996
A computer system has a $$4K$$ word cache organized in block set associative manner with $$4$$ blocks per set, $$64$$ wo...
GATE CSE 1995
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate...
GATE CSE 1995
A $$ROM$$ is used to store a truth table for a binary multiplier unit that will multiply two $$4$$ bit numbers. The size...
GATE CSE 1995

## Marks 2

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Consider a computer system with a byte-addressable primary memory of size 232&nbsp;bytes. Assume the computer system has...
GATE CSE 2021 Set 1
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associat...
GATE CSE 2020
The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capaci...
GATE CSE 2018
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The laten...
GATE CSE 2016 Set 2
The width of the physical address on a machine is $$40$$ bits. The width of the tag field in a $$512$$ $$KB$$ $$8$$-way ...
GATE CSE 2016 Set 2
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When...
GATE CSE 2014 Set 2
The memory access time is $$1$$ nanosecond for a read operation with a hit in cache, $$5$$ nanoseconds for a read operat...
GATE CSE 2014 Set 3
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of t...
GATE CSE 2014 Set 2
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the...
GATE CSE 2014 Set 2
A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. Th...
GATE CSE 2014 Set 2
A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \... GATE CSE 2013 A computer has a$$256K$$Byte,$$4$$-way set associative, write back data cache with block size of$$32$$Bytes. T... GATE CSE 2012 A computer has a$$256K$$Byte,$$4$$-way set associative, write back data cache with block size of$$32$$Bytes. T... GATE CSE 2012 An$$8KB$$direct-mapped write-back cache is organized as multiple blocks, each of size$$32$$-bytes. The processor gene... GATE CSE 2011 A computer system has an$$L1$$cache, an$$L2$$cache, and a main memory unit connected as shown below. The block size ... GATE CSE 2010 A computer system has an$$L1$$cache, an$$L2$$cache, and a main memory unit connected as shown below. The block size ... GATE CSE 2010 Consider a$$4$$-way set associative cache (initially empty) with total$$16$$cache blocks. The main memory consists of... GATE CSE 2009 For inclusion to hold between two cache levels$$L1$$and$$L2$$in a multilevel cache hierarchy, which of the following... GATE CSE 2008 Consider a machine with a byte addressable main memory of$${2^{16}}$$bytes. Assume that a direct mapped data cache con... GATE CSE 2007 Consider a machine with a byte addressable main memory of$${2^{16}}$$bytes. Assume that a direct mapped data cache con... GATE CSE 2007 Consider two cache organization: The first one is$$32KB2$$-way set associate with$$32$$-byte block size. The... GATE CSE 2006 Consider two cache organization: The first one is$$32KB2$$-way set associate with$$32$$-byte block size. The... GATE CSE 2006 A$$CPU$$has a cache with block size$$64$$bytes. The main memory has$$k$$banks, each bank being$$c$$bytes wide. C... GATE CSE 2006 Consider a direct mapped cache of size$$32KB$$with block size$$32$$bytes. The$$CPU$$generates$$32$$bit addr... GATE CSE 2005 Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced,... GATE CSE 2004 A block -set associative cache memory consists of$$128$$blocks divided into four block sets. The main memory consists ... GATE CSE 1990 ## Marks 5 More A$$CPU$$has$$32$$-bit memory address and a$$256KB$$cache memory. The cache is organized as a$$4-way set ass...
GATE CSE 2001
A computer system has a three level memory hierarchy, with access time and hit ratios as shown below: (i) What shou...
GATE CSE 1996

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