The circuit shown in the Fig. is in steady state, when the switch is closed at $$t=0.$$ Assuming that the inductance is ideal, the current through the inductor at $$t = {0^ + }$$ equals

The $$RL$$ circuit of the figure is fed from a constant magnitude, variable frequency sinusoidal voltage source $${V_{IN.}}$$ At $$100Hz,$$ the $$R$$ and $$L$$ elements each have a voltage drop $${u_{RMS}}.$$ If the frequency of the source is changed to $$50Hz,$$ then new voltage drop across $$R$$ is

In the Fig. given below, the initial capacitor voltage is zero. The switch is closed at $$t = 0.$$ the final steady-state voltage across the capacitor is

In the figure given below the value of $$R$$ is