The current in the circuit shown in figure is

A fixed capacitor of reactance –$$j0.02$$ $$\Omega $$ is connected in parallel across a series combination of a fixed inductor of reactance $$j0.01$$ $$\Omega $$ and a variable resistance $$R.$$ As $$R$$ is varied from zero to infinity, the locus diagram of the admittance of this $$L-C-R$$ circuit will be

The voltage phasor of a circuit is $$10\angle {15^0}\,V$$ and the current phasor is $$2\,\,\angle - {45^0}A.$$ The active and the reactive powers in the circuit are

For a dual $$ADC$$ type $$3\,\,{1 \over 2}$$ digit $$DVM$$, the reference voltage is $$100mV$$ and the first integration time is set to $$300$$$$ms$$. For some input voltage, the ''deintegration'' period is $$370.2ms$$. The $$DVM$$ will indicate