The input signal $${V_{in}}$$ shown in the figure is a $$1$$ $$kHz$$ square wave voltage that alternates between $$+7V$$ and $$-7V$$ with a $$50\% $$ duty cycle. Both transistors have the same current gain, which is large. The circuit delivers power to the load resistor $${R_L}.$$ What is the efficiency of this circuit for the given input? Choose the closest answer.

The circuit shown in figure is

The three terminal linear voltage regular is connected to a $$10\Omega $$ load resistor as shown in the figure. If $${V_{in}}$$ is $$10$$ $$V,$$ what is the power dissipated in the transistor

The common emitter forward current gain of the transistor shown is $${\beta _p} = 100.$$ The transistor is operating in