1
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
The system shown in figure below GATE EE 2007 Control Systems - Block Diagram and Signal Flow Graph Question 3 English 1
can be reduced to the form GATE EE 2007 Control Systems - Block Diagram and Signal Flow Graph Question 3 English 2
With
A
$$X = {C_0}s + {C_1},\,\,Y = 1/\left( {{s^2} + {a_0}s + {a_1}} \right),\,z = {b_0}s + {b_1}$$
B
$$X = 1,\,\,Y = \left( {{c_0}s + {c_1}} \right)/\left( {{s^2} + {a_0}s + {a_1}} \right),\,z = {b_0}s + {b_1}$$
C
$$X = {C_1}s + {C_0},\,\,Y = \left( {{b_1}s + {b_0}} \right)/\left( {{s^2} + {a_1}s + {a_0}} \right),\,z = 1$$
D
$$X = {C_1}s + {C_0},\,\,Y = 1/\left( {{s^2} + {a_1}s + {a_0}} \right),\,z = {b_1}s + {b_0}$$
2
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
The associated figure shows the two types of rotate right instruction $${R_1},\,{R_2}$$ available in a microprocessor where Register is a $$8$$-bit register and $$C$$ is the carry bit. The rotate left instructions $$L1$$ and $$L2$$ are similar except that $$C$$ now links the most significant bit of Register instead of the least significant one. GATE EE 2007 Digital Electronics - Microprocessor Question 10 English

Such a division can be correctly performed by the following set of operations

A
$$L2,R2,R1$$
B
$$L2, R1, R2$$
C
$$R2, L1, R1$$
D
$$R1, L2, R2$$
3
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
The associated figure shows the two types of rotate right instruction $${R_1},\,{R_2}$$ available in a microprocessor where Register is a $$8$$-bit register and $$C$$ is the carry bit. The rotate left instructions $$L1$$ and $$L2$$ are similar except that $$C$$ now links the most significant bit of Register instead of the least significant one. GATE EE 2007 Digital Electronics - Microprocessor Question 11 English

Suppose Register contains the $$2's$$ complement number $$11010110.$$ If this number is delivered by $$2$$ the answer should be

A
$$01101011$$
B
$$10010101$$
C
$$11101001$$
D
$$11101011$$
4
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
In an $$8085$$ $$A$$ microprocessor based system, it is desired to increment the contents of memory location whose address is available in $$(D,E)$$ register pair and store the result in same location. The sequence of instructions is
A
$$XCHG,\,\,INR\,\,\,M$$
B
$$XCHG,\,\,INX\,\,\,H$$
C
$$INX\,\,D,\,\,XCHG$$
D
$$INR\,\,M,\,\,XCHG$$
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