1
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
Which one of the following statements regarding the $$INT$$ (interrupt) and the $$BRQ$$ (bus request) pins in a $$CPU$$ is true?
A
The $$BRQ$$ pin is sampled after every instruction cycle, but the $$INT$$ is sampled after every machine cycle
B
Both $$INT$$ and $$BRQ$$ are sampled after every machine cycle
C
The $$INT$$ pin is sampled after every instruction cycle, but the $$BRQ$$ is sampled after every machine cycle
D
Both $$INT$$ and $$BRQ$$ are sampled after every instruction cycle
2
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
The associated figure shows the two types of rotate right instruction $${R_1},\,{R_2}$$ available in a microprocessor where Register is a $$8$$-bit register and $$C$$ is the carry bit. The rotate left instructions $$L1$$ and $$L2$$ are similar except that $$C$$ now links the most significant bit of Register instead of the least significant one. GATE EE 2007 Digital Electronics - Microprocessor Question 10 English

Such a division can be correctly performed by the following set of operations

A
$$L2,R2,R1$$
B
$$L2, R1, R2$$
C
$$R2, L1, R1$$
D
$$R1, L2, R2$$
3
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
The $$R-L-C$$ series circuit shown is supplied from a variable frequency voltage source. The admittance $$-$$ locus of the $$R-L$$ $$-C$$ network at terminals $$AB$$ for increasing frequency $$\omega $$ is GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 15 English
A
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 15 English Option 1
B
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 15 English Option 2
C
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 15 English Option 3
D
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 15 English Option 4
4
GATE EE 2007
MCQ (Single Correct Answer)
+2
-0.6
In the figure given below, all phasors are with reference to the potential at point $$''O''.$$ The locus of voltage phasor $${V_{YX}}$$ as $$R$$ is varied from zero to infinity is shown by GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 14 English
A
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 14 English Option 1
B
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 14 English Option 2
C
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 14 English Option 3
D
GATE EE 2007 Electric Circuits - Sinusoidal Steady State Analysis Question 14 English Option 4