Which of the following are NOT true in a pipelined processor?
$$1.$$ Bypassing can handle all RAW hazards
$$2.$$ Register renaming can eliminate all register carried WAR hazards
$$3.$$ Control hazard penalties can be eliminated by dynamic branch prediction.

For all delayed conditional branch instructions, irrespective of whether the condition evaluate true or false,

Which of the following is/are true of the auto increment addressing mode?
$$1.$$ It is useful in creating self relocating code
$$2.$$ If it is included in an Instruction Set Architecture, then an additional $$ALU$$ is required for effective address calculation
$$3.$$ The amount of increment depends on the size of the data item accessed.

Which of the following must be true for the $$RFE$$ (Return From Exception) instruction on a general purpose processor?
$$1.$$ It must be a trap instruction
$$2.$$ It must be a privileged instruction
$$3.$$ An exception cannot be allowed to occur during execution of an $$RFE$$ instruction.