A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:
$$ * \,\,\,\,\,\,$$ Bits 30-31 are used to index into the first level page table
$$ * \,\,\,\,\,\,$$ Bits 21-29 are used to index into the second level page table
$$ * \,\,\,\,\,\,$$ Bits 12-20 are used to index into the third level page table, and
$$ * \,\,\,\,\,\,$$ Bits 0-11 are used as offset within the page

The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively

Which of the following is NOT true of deadlock prevention and deadlock avoidance schemes?

For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to

The data blocks of a very large file in the Unix file system are allocated using