1
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
In an instruction execution pipeline, the earliest that the data $$TLB$$ (Translation Look aside Buffer) can be accessed is
A
Before effective address calculation has started
B
During effective address calculation
C
After effective address calculation has completed
D
After data cache lookup has completed
2
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
The following code is to run on a pipelined processor with one branch delay slot
$$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr} $$

Which of the instructions $${{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$ or $${{\rm I}_4}$$ can legitimately occupy the delay slot without any other program modification?

A
$${{\rm I}_1}$$
B
$${{\rm I}_2}$$
C
$${{\rm I}_3}$$
D
$${{\rm I}_4}$$
3
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
$$1.\,\,\,\,$$ Function locals and parameters
$$2.\,\,\,\,$$ Register saves and restores
$$3.\,\,\,\,$$ Instruction fetches
A
$$1$$ only
B
$$2$$ only
C
$$3$$ only
D
$$1,2$$ and $$3$$
4
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
For inclusion to hold between two cache levels $$L1$$ and $$L2$$ in a multilevel cache hierarchy, which of the following are necessary?

$$1.$$ $$L1$$ must be a write-through cache
$$2.$$ $$L2$$ must be a write-through cache
$$3.$$ The associativity of $$L2$$ must be greater than that of $$L1$$
$$4.$$ The $$L2$$ cache must be at least as large as the $$L1$$ cache

A
$$4$$ only
B
$$1$$ and $$2$$ only
C
$$1,2$$ and $$4$$ only
D
$$1,2,3$$ and $$4$$
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