Which of the following must be true for the $$RFE$$ (Return From Exception) instruction on a general purpose processor?
$$1.$$ It must be a trap instruction
$$2.$$ It must be a privileged instruction
$$3.$$ An exception cannot be allowed to occur during execution of an $$RFE$$ instruction.

In an instruction execution pipeline, the earliest that the data $$TLB$$ (Translation Look aside Buffer) can be accessed is

The following code is to run on a pipelined processor with one branch delay slot
$$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr} $$

Which of the instructions $${{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$ or $${{\rm I}_4}$$ can legitimately occupy the delay slot without any other program modification?

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
$$1.\,\,\,\,$$ Function locals and parameters
$$2.\,\,\,\,$$ Register saves and restores
$$3.\,\,\,\,$$ Instruction fetches