A TTL NOT gate circuit is shown in figure. Assuming $${V_{BE}} = 0.7\,v$$ of both the transistors, if $${V_i} = 3.0\,V,$$ then the states of the two transistors will be

A software delay subroutine is written as given below:

How many times $$DCR$$ $$L$$ instruction will be executed?

A $$400V$$, $$50$$ $$Hz,$$ three phase balanced source supplies power to a star connected load whose rating is $$12\,\,\angle 3\,\,kVA,$$ $$0.8$$ $$pf$$ (lag). The rating $$($$in $$kVAR)$$ of the delta connected (capacitive) reactive power bank necessary to bring the $$pf$$ to unity is

The circuit shown in the figure is energized by a sinusoidal voltage source $${V_1}$$ at a frequency which causes resonance with a current of $${\rm I}$$.

The phasor diagram which is applicable to this circuit is