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## Marks 1

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Consider the 2-bit multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and D, the values for A0, A1, A2...
GATE ECE 2022
Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is ...
GATE ECE 2017 Set 2
A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are the bits to be added while ...
GATE ECE 2016 Set 2
In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by
GATE ECE 2014 Set 2
The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number ...
GATE ECE 2012
The logic function implemented by the circuit below is (ground implies a logic "0" ...
GATE ECE 2011
The Boolean function f implemented in the figure using two input multiplexers is ...
GATE ECE 2005
With out any additional circuitry, an 8:1 MUX can be used to obtain
GATE ECE 2003
A 2-bit binary multiplier can be implemented using
GATE ECE 1997
The output of the circuit shown in figure is equal to ...
GATE ECE 1995
The logic realized by the circuit shown in figure is ...
GATE ECE 1992
The minimum function that can detect a "divisible by 3" 8421 BCD code digit (representation is D8 D4 D2 D1) is given b...
GATE ECE 1990

## Marks 2

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A four-variable Boolean function is realized using 4 $$\times$$ 1 multiplexers as shown in the figure. The minimized ...
GATE ECE 2018
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (F...
GATE ECE 2017 Set 2
A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is ...
GATE ECE 2017 Set 2
Identify the circuit below. ...
GATE ECE 2016 Set 1
For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are 2 ns, 1.5 ns and 1 ns, resp...
GATE ECE 2016 Set 3
The functionality implemented by the circuit below is ...
GATE ECE 2016 Set 1
A 1-to-8 demultiplexer with data input D$$_{in}$$ , address inputs S$$_{0}$$, S$$_{1}$$, S$$_{2}$$ (with S$$_{0}$$ as th...
GATE ECE 2015 Set 2
An 8-to-1 multiplexer is used to implement a logical function Y as shown in the figure. The output Y is given by ...
GATE ECE 2014 Set 4
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagatio...
GATE ECE 2014 Set 4
If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diag...
GATE ECE 2014 Set 3
In the circuit shown, 𝑊𝑊 and 𝑌𝑌 are MSBs of the control inputs. The output 𝐹𝐹 is given by ...
GATE ECE 2014 Set 3
The Boolean function realized by the logic circuit shown is ...
GATE ECE 2010
What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate?
GATE ECE 2009
For the circuit shown in the following figure $${I_0}$$ - $${I_3}$$ are inputs to the 4:1 multiplexer R(MSB) and S are c...
GATE ECE 2008
In the following circuit, X is given by ...
GATE ECE 2007
The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer is
GATE ECE 2004
GATE ECE 2002

## Marks 8

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The circuit diagram of a 2 bit A to D converter is shown in figure below. The combinational logic is to be disigned to p...
GATE ECE 1987

## Marks 10

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A ROM is to be used to implement the Boolean functions given below: $${F_1}$$$$(A,\,B,\,C,\,D) = ABCD + \bar A\,\overli... GATE ECE 1995 A Boolean function, F , given as sum of product (SOP) terms as F=$$\sum {} $$m(3,4,5,6) with A,B, and C as inputs. The ... GATE ECE 1994 Signals A,B,C,D and$$\overline D  are available. Using a single 8 - to - 1 multiplexer and no other gate, implement t...
GATE ECE 1993
A chemical reactor has three sensors indicating the following conditions:- (1) Pressure (P) is low or high' (2) Temper...
GATE ECE 1989

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