In the single stage transistor amplifier circuit shown in figure, the capacitor $${C_E}$$ is removed. Then the ac small signal midband voltage gain of the amplifier

A sample-and-hold $$(S/H)$$ circuit, having a holding capacitor of $$0.1$$ $$nF,$$ is used at the input of an $$ADC$$ (analog-to-digital converter). The conversion time of the $$ADC$$ is $$1\,\,\mu \sec ,$$ and during this time, the capacitor should not lose more than $$0.5\% $$ of the charge put across it during the sampling time. The maximum value of the input signal to the $$S/H$$ circuit is $$5V.$$ The leakage current of the $$S/H$$ circuit should be less than

An $$N$$-channel $$JFET$$ having a pinch-off voltage $$\left( {{V_P}} \right)$$ of $$-5V$$ shows a transconductance (gm) of $$1$$ $$mA/V$$ when the applied Gate to source voltage $$\left( {{V_{GS}}} \right)$$ is $$-3V.$$ Its maximum transconductance (in $$mA/V$$) is

The polar plot of a type-$$1, 3$$-pole, open-loop system is shown in Fig. below. The closed loop system is