In standard $$TTL$$ gates, the totem pole output stage is primarily used to

In a digital combinational circuit with $$4$$ inputs $$(A, B, C, D),$$ it is required to obtain an output of logical $$1$$ only for the input combination

$$(A = 1; B = C = D = 0).$$ It is known that the following combinations of input are forbidden:

$$ABCD = 1010, 1011, 1100, 1101, 1110, 1111$$
Evaluate the logical expression for the output and realize the same with two input $$NAND$$ gates. Assume that complements of inputs are not available.

The switch in the following circuit, shown in Fig. has been connected to the $$12V$$ source for a long time. At $$t=0,$$ the switch is thrown to $$24$$ $$V$$.

$$L = 2\,H,\,\,{R_1} = 10\,\Omega ,\,\,{R_2} = 2\,\Omega ,\,\,C = 0.25\,\mu F$$
$$(a)$$ Determine $${i_L}\left( 0 \right)$$ and $${V_C}\left( 0 \right)$$
$$(b)$$ Write the differential equation governing $${V_C}\left( t \right)$$ for $$t>0$$
$$(c)$$ Compute the steady state value of $${V_C}\left( t \right)$$

A circuit consisting of a single resistor $$R$$ and an inductor $$L$$ in series is driven by a $$25$$ $$V$$ $$rms,$$ $$50$$ $$Hz$$ sinusoidal voltage source. A capacitor is to be placed in parallel with the source to improve the power factor. Given that the average power dissipated in the $$R$$ is $$100$$ $$W$$ and that the reactive power delivered to the $$L$$ is $$75$$ $$VAR,$$ what value of $$C$$ will yield a $$0.9$$ $$p.f.$$ lagging as seen by the source?