1
GATE EE 1998
MCQ (Single Correct Answer)
+1
-0.3
In standard $$TTL$$ gates, the totem pole output stage is primarily used to
A
Increase the noise margin of the gate
B
Decrease the output switching delay
C
Facilitate a wired OR logic connection
D
Increase the output impedance of the circuit
2
GATE EE 1998
Subjective
+5
-0
$$(a)$$ Construct the truth table for the circuit given in Figure $${Q_1},{Q_2}$$ and $${Q_3}$$ are outputs and the clock pulses are the inputs. Unused $$JK$$ inputs are assumed to be at logic $$1.$$ All flip flops are reset at power $$ON$$. GATE EE 1998 Digital Electronics - Sequential Circuits Question 6 English
$$(b)$$ Sketch the output waveforms at $${Q_1},{Q_2}$$ and $${Q_3}$$.
$$(c)$$ What function does this circuit perform.

3
GATE EE 1998
MCQ (Single Correct Answer)
+1
-0.3
A sinusoidal source of voltage $$V$$ and frequency $$f$$ is connected to a series circuit of variables resistance, $$R$$ and a fixed reactance, $$X.$$ The locus of the tip of the current phasor, $$I$$, as $$R$$ is varied from $$0$$ to $$\infty $$ is
A
a semicircle with a diameter of $$V/X.$$
B
a straight line with a slope of $$R/X.$$
C
an ellipse with $$V/R$$ as major axis.
D
a circle of radius $$R/X$$ and origin at $$\left( {0,\,\,\,V/2} \right).$$
4
GATE EE 1998
Subjective
+5
-0
Determine the impedance seen by the source $${V_s} = 24\angle {0^0}$$ in the network shown in Fig. GATE EE 1998 Electric Circuits - Sinusoidal Steady State Analysis Question 8 English
EXAM MAP