1
GATE CSE 2006
+1
-0.3
For which one of the following reasons does Internet Protocol (IP) use the time-to-live (TTL) field in the IP datagram header?
A
Ensure packets reach destination within that time
B
Discard packets that reach later than that time
C
Prevent packets from looping indefinitely
D
Limit the time for which a packet gets queued in intermediate routers.
2
GATE CSE 2006
+2
-0.6
Two computers C1 and C2 are configured as follows. C1 has IP address 203.197.2.53 and netmask 255.255.128.0. C2 has IP address 203.197.75.201 and netmask 255.255.192.0. which one of the following statements is true?
A
C1 and C2 both assume they are on the same network
B
C2 assumes C1 is on same network, but C1 assumes C2 is on a different network
C
C1 assumes C2 is on same network, but C2 assumes C1 is on a different network
D
C1 and C2 both assume they are on different networks
3
GATE CSE 2006
+2
-0.6
Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are added is
A
\eqalign{ & {a_2}{b_2} + {a_2}{a_1}{b_1} + {a_2}{a_1}{a_0}{b_0} + {a_2}{a_0}{b_1}{b_2}{b_1} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_0}{b_2}{b_1}{b_0} \cr}
B
\eqalign{ & {a_2}{b_2} + {a_2}{b_1}{b_0} + {a_2}{a_1}{b_1}{b_0} + {a_1}{a_0}{b_2}{b_1} + {a_1}{a_0}{b_2} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_2}{b_0}{b_1}{b_0} \cr}
C
$${a_2} + {b_2} + \left( {{a_2} \oplus {b_2}} \right)\left( {{a_1} + {b_1} + \left( {{a_1} \oplus {b_1}} \right)\left( {{a_0} + {b_0}} \right)} \right)$$
D
\eqalign{ & {a_2}{b_2} + \overline {{a_2}} {a_1}{b_1} + \overline {{a_2}{a_1}} {a_0}{b_0} + \cr & {a_2}{a_0}\overline {{b_1}} {b_0} + {a_1}\overline {{b_2}} {b_1} + \overline {{a_1}} {a_0}\overline {{b_2}} {b_0} + {a_0}\overline {{b_2}{b_1}} {b_0} \cr}
4
GATE CSE 2006
+2
-0.6
A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks are mapped on consecutive banks with wrap-around. All the $$k$$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the $$k$$ banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $$k/2$$ $$ns.$$ The latency of one bank access is $$80$$ $$ns.$$ If $$c=2$$ and $$k=24,$$ then latency of retrieving a cache block starting at address zero from main memory is
A
$$92$$ $$ns$$
B
$$104$$ $$ns$$
C
$$172$$ $$ns$$
D
$$184$$ $$ns$$
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