A CPU has five stages pipeline and runs at $$1$$ $$GHz$$ frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instruction following a conditional branch until the branch outcome is known. A program executes $${10^9}$$ instructions out of which $$20$$% are conditional branches. If each instruction takes one cycle to complete on average, then total execution time of the program is

A $$CPU$$ has $$24$$-bit instructions. A program starts at address $$300$$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

Assume that the content of memory location $$3000$$ is $$10$$ and the content of the register $$R3$$ is $$2000$$. The content of each of the memory locations from $$2000$$ to $$2010$$ is $$100.$$ The program is loaded from the memory location $$1000.$$ All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

Assume that the content of memory location $$3000$$ is $$10$$ and the content of the register $$R3$$ is $$2000$$. The content of each of the memory locations from $$2000$$ to $$2010$$ is $$100.$$ The program is loaded from the memory location $$1000.$$ All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is $$32$$ bits. If an interrupt occurs during the execution of the instruction $$''INC$$ $$R3'',$$ what return address will be pushed on to the stack?