A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks are mapped on consecutive banks with wrap-around. All the $$k$$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the $$k$$ banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $$k/2$$ $$ns.$$ The latency of one bank access is $$80$$ $$ns.$$ If $$c=2$$ and $$k=24,$$ then latency of retrieving a cache block starting at address zero from main memory is

Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_1}$$ is

Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are added is

Let T be a depth first search tree in an undirected graph G. Vertices u and v are leaves of this tree T. The degrees of both u and v in G are at least 2. which one of the following statements is true?