1
GATE CSE 2006
+2
-0.6
Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are added is
A
\eqalign{ & {a_2}{b_2} + {a_2}{a_1}{b_1} + {a_2}{a_1}{a_0}{b_0} + {a_2}{a_0}{b_1}{b_2}{b_1} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_0}{b_2}{b_1}{b_0} \cr}
B
\eqalign{ & {a_2}{b_2} + {a_2}{b_1}{b_0} + {a_2}{a_1}{b_1}{b_0} + {a_1}{a_0}{b_2}{b_1} + {a_1}{a_0}{b_2} \cr & + {a_1}{a_0}{b_2}{b_0} + {a_2}{b_0}{b_1}{b_0} \cr}
C
$${a_2} + {b_2} + \left( {{a_2} \oplus {b_2}} \right)\left( {{a_1} + {b_1} + \left( {{a_1} \oplus {b_1}} \right)\left( {{a_0} + {b_0}} \right)} \right)$$
D
\eqalign{ & {a_2}{b_2} + \overline {{a_2}} {a_1}{b_1} + \overline {{a_2}{a_1}} {a_0}{b_0} + \cr & {a_2}{a_0}\overline {{b_1}} {b_0} + {a_1}\overline {{b_2}} {b_1} + \overline {{a_1}} {a_0}\overline {{b_2}} {b_0} + {a_0}\overline {{b_2}{b_1}} {b_0} \cr}
2
GATE CSE 2006
+2
-0.6
A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks are mapped on consecutive banks with wrap-around. All the $$k$$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the $$k$$ banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $$k/2$$ $$ns.$$ The latency of one bank access is $$80$$ $$ns.$$ If $$c=2$$ and $$k=24,$$ then latency of retrieving a cache block starting at address zero from main memory is
A
$$92$$ $$ns$$
B
$$104$$ $$ns$$
C
$$172$$ $$ns$$
D
$$184$$ $$ns$$
3
GATE CSE 2006
+2
-0.6
Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_1}$$ is

A
$$2.4$$ $$ns$$
B
$$2.3$$ $$ns$$
C
$$1.8$$ $$ns$$
D
$$1.7$$ $$ns$$
4
GATE CSE 2006
+2
-0.6
Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_2}$$ is

A
$$2.4$$ $$ns$$
B
$$2.3$$ $$ns$$
C
$$1.8$$ $$ns$$
D
$$1.7$$ $$ns$$
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