Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

Assume that the content of memory location $$3000$$ is $$10$$ and the content of the register $$R3$$ is $$2000$$. The content of each of the memory locations from $$2000$$ to $$2010$$ is $$100.$$ The program is loaded from the memory location $$1000.$$ All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location $$2010$$ is

A $$CPU$$ has $$24$$-bit instructions. A program starts at address $$300$$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?

A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks are mapped on consecutive banks with wrap-around. All the $$k$$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the $$k$$ banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $$k/2$$ $$ns.$$ The latency of one bank access is $$80$$ $$ns.$$ If $$c=2$$ and $$k=24,$$ then latency of retrieving a cache block starting at address zero from main memory is

A CPU has five stages pipeline and runs at $$1$$ $$GHz$$ frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instruction following a conditional branch until the branch outcome is known. A program executes $${10^9}$$ instructions out of which $$20$$% are conditional branches. If each instruction takes one cycle to complete on average, then total execution time of the program is