1
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Consider the system described by the following state space equations $$$\eqalign{ & \left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] = \left[ {\matrix{ 0 & 1 \cr { - 1} & { - 1} \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] + \left[ {\matrix{ 0 \cr 1 \cr } } \right]u; \cr & y = \left[ {\matrix{ 1 & 0 \cr } } \right]\left[ {\matrix{ {{x_1}} \cr {{x_2}} \cr } } \right] \cr} $$$

If $$u$$ unit step input, then the steady state error of the system is

A
$$0$$
B
$$1/2$$
C
$$2/3$$
D
$$1$$
2
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
Two monoshot multivibrators, one positive edge triggered $$\left( {{M_1}} \right)$$ and another negative edge triggered $$\left( {{M_2}} \right)$$ are connected as shown in figure. GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 8 English

The monoshots $${{M_1}}$$ and $${{M_2}}$$ when triggered produce pulses of width $${{T_1}}$$ and $${{T_2}}$$ respectively, where $${T_1} > {T_2}.$$ The steady state output voltage $${V_0}$$ of the circuit is

A
GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 8 English Option 1
B
GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 8 English Option 2
C
GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 8 English Option 3
D
GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 8 English Option 4
3
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+2
-0.6
A $$3$$-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is $${000_2}.$$ The output is pulled high. The output of the circuit follows the sequence GATE EE 2014 Set 3 Digital Electronics - Combinational Circuits Question 7 English
A
$${{\rm I}_0},\,1,\,1,\,{{\rm I}_1},\,{{\rm I}_3},\,1,\,1,\,{{\rm I}_2}$$
B
$${{\rm I}_0},\,1,\,{{\rm I}_1},\,1,\,{{\rm I}_2},\,{{\rm I}_3},\,1$$
C
$$1,\,{{\rm I}_0},\,1,\,{{\rm I}_1},\,{{\rm I}_2},\,1,\,{{\rm I}_3},\,1$$
D
$${{\rm I}_0},\,{{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3},\,{{\rm I}_0},\,{{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$
4
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state. GATE EE 2014 Set 3 Digital Electronics - Sequential Circuits Question 21 English

The logic gate represented by the state diagram is

A
$$XOR$$
B
$$OR$$
C
$$AND$$
D
$$NAND$$
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