1
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the output representing the state. GATE EE 2014 Set 3 Digital Electronics - Sequential Circuits Question 21 English

The logic gate represented by the state diagram is

A
$$XOR$$
B
$$OR$$
C
$$AND$$
D
$$NAND$$
2
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
In $$8085A$$ microprocessor, the operation performed by the instruction $$LHLD$$ $${2100_H}$$ is
A
$$\left( H \right) \leftarrow {21_H},\,\left( L \right) \leftarrow {00_H}$$
B
$$\left( H \right) \leftarrow M\left( {{{2100}_H}} \right),\,\left( L \right) \leftarrow M\left( {{{2101}_H}} \right)$$
C
$$\left( H \right) \leftarrow M\left( {{{2101}_H}} \right),\,\left( L \right) \leftarrow M\left( {{{2100}_H}} \right)$$
D
$$\left( H \right) \leftarrow {00_H},{\mkern 1mu} \left( L \right) \leftarrow {21_H}$$
3
GATE EE 2014 Set 3
Numerical
+2
-0
The Norton’s equivalent source in amperes as seen into the terminals X and Y is _______. GATE EE 2014 Set 3 Electric Circuits - Network Theorems Question 24 English
Your input ____
4
GATE EE 2014 Set 3
MCQ (Single Correct Answer)
+1
-0.3
A non-ideal voltage source VS has an internal impedance of ZS. If a purely resistive load is to be chosen that maximizes the power transferred to the load, its value must be
A
0
B
real part of ZS
C
magnitude of ZS
D
complex conjugate of ZS
EXAM MAP