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GATE EE 2010

MCQ (Single Correct Answer)

-0.6

When a $$''CALL$$ $$addr'$$ instruction is executed, the $$CPU$$ carries out the following sequential operations internally.

Note:
$$(R)$$ means content of register $$R$$
$$\left( {\left( R \right)} \right)$$ means content of memory locating pointed by $$R$$
$$PC$$ means Program Counter
$$SP$$ means Stack Pointer

$$\eqalign{ & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr} $$

$$\eqalign{ & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr} $$

$$\eqalign{ & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr} $$

$$\eqalign{ & \left( {\left( {SP} \right)} \right) \leftarrow \left( {PC} \right) \cr & \left( {SP} \right)\,\,\,\,\,\,\,incremented \cr & \left( {PC} \right)\,\,\,\,\,\, \leftarrow \left( {Addr} \right) \cr} $$

GATE EE 2010

MCQ (Single Correct Answer)

-0.6

If the 12 Ω resistor draws a current of 1A as shown in the figure, the value of resistance R is GATE EE 2010 Electric Circuits - Network Elements Question 46 English

GATE EE 2010

MCQ (Single Correct Answer)

-0.3

As shown in the figure, a 1 Ω resistance is connected across a source that has a load line v + i = 100. The current through the resistance is GATE EE 2010 Electric Circuits - Network Elements Question 55 English

GATE EE 2010 Electric Circuits - Network Elements Question 55 English

25 A

50 A

100 A

200 A

GATE EE 2010

MCQ (Single Correct Answer)

-0.6

The two-port network P shown in the figure has ports 1 and 2, denoted by terminals (a, b) and (c, d), respectively. It has an impedance matrix Z with parameters denoted by z_ij. A 1 Ω resistor is connected in series with the network at port 1 as shown in the figure. The impedance matrix of the modified two-port network (shown as a dashed box) is GATE EE 2010 Electric Circuits - Two Port Networks Question 12 English

GATE EE 2010 Electric Circuits - Two Port Networks Question 12 English

$$\begin{pmatrix}z_{11}+1&z_{12}+1\\z_{21}&z_{22}+1\end{pmatrix}$$

$$\begin{pmatrix}z_{11}+1&z_{12}\\z_{21}&z_{22}+1\end{pmatrix}$$

$$\begin{pmatrix}z_{11}+1&z_{12}\\z_{21}&z_{22}\end{pmatrix}$$

$$\begin{pmatrix}z_{11}+1&z_{12}\\z_{21}+1&z_{22}\end{pmatrix}$$

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