1
GATE EE 2023
Numerical
+2
-0

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is ___________.

GATE EE 2023 Digital Electronics - Logic Gates Question 1 English

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2
GATE EE 2023
Numerical
+2
-0

In a given 8-bit general purpose micro-controller there are following flags.

C-Carry, A-Auxiliary Carry, O-Overflow flag, P-Parity (0 for even, 1 for odd)

R$$_0$$ and R$$_1$$ are the two general purpose registers of the micro-controller.

After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be _________.

MOV R0, +0x60

MOV R1, +0x46

ADD R0, R1

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3
GATE EE 2023
Numerical
+1
-0

The value of parameters of the circuit shown in the figure are

$${R_1} = 2\Omega ,{R_2} = 2\Omega ,{R_3} = 3\Omega ,L = 10$$ mH, $$C = 100$$ $$\mu$$F

For time t < 0, the circuit is at steady state with the switch 'K' in closed condition. If the switch is opened at t = 0, the value of the voltage across the inductor (V$$_L$$) at t = 0$$^+$$ in Volts is ___________ (Round off to 1 decimal place).

GATE EE 2023 Electric Circuits - Sinusoidal Steady State Analysis Question 3 English

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4
GATE EE 2023
Numerical
+1
-0

For the circuit shown in the figure, $$V_1=8$$ V, DC and $$I_1=8$$ A, DC. The voltage $$V_{ab}$$ in Volts is __________ (Round off to 1 decimal place).

GATE EE 2023 Electric Circuits - Network Theorems Question 2 English

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