1
GATE EE 2023
MCQ (Single Correct Answer)
+2
-0.67

Consider a lead compensator of the form

$$K(s) = {{1 + {s \over a}} \over {1 + {s \over {\beta a}}}},\beta > 1,a > 0$$

The frequency at which this compensator produces maximum phase lead is 4 rad/s. At this frequency, the gain amplification provided by the controller, assuming asymptotic Bode-magnitude plot of $$K(s)$$, is 6 dB. The values of $$a,\beta$$, respectively, are

A
1, 16
B
2, 4
C
3, 5
D
2.66, 2.25
2
GATE EE 2023
Numerical
+2
-0.67

Consider the state-space description of an LTI system with matrices

$$A = \left[ {\matrix{ 0 & 1 \cr { - 1} & { - 2} \cr } } \right],B = \left[ {\matrix{ 0 \cr 1 \cr } } \right],C = \left[ {\matrix{ 3 & { - 2} \cr } } \right],D = 1$$

For the input, $$\sin (\omega t),\omega > 0$$, the value of $$\omega$$ for which the steady-state output of the system will be zero, is ___________ (Round off to the nearest integer).

Your input ____
3
GATE EE 2023
MCQ (Single Correct Answer)
+2
-0.67

An 8 bit ADC converts analog voltage in the range of 0 to +5 V to the corresponding digital code as per the conversion characteristics shown in figure. For $$V_{in}=1.9922~V$$, which of the following digital output, given in hex, is true?

GATE EE 2023 Digital Electronics - Analog to Digital and Digital to Analog Converter Question 1 English

A
64H
B
65H
C
66H
D
67H
4
GATE EE 2023
Numerical
+2
-0.67

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change with clock, is ___________.

GATE EE 2023 Digital Electronics - Logic Gates Question 1 English

Your input ____
EXAM MAP
Medical
NEETAIIMS
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
Civil Services
UPSC Civil Service
Defence
NDA
Staff Selection Commission
SSC CGL Tier I
CBSE
Class 12