1
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
Consider the following processor design characteristics.

$$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only
$$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format
$$\,\,\,{\rm I}{\rm I}{\rm I}.\,\,\,\,\,$$ Hardwired control unit

Which of the characteristics above are used in the design of a $$RISC$$ processor?

A
$${\rm I}$$ and $${\rm II}$$ only
B
$${\rm I}$$$${\rm I}$$ and $${\rm III}$$ only
C
$${\rm I}$$ and $${\rm III}$$ only
D
$${\rm I},$$ $${\rm II}$$ and $${\rm III}$$ only
2
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
The following are some events that occur after a device controller issues an interrupt while process $$L$$ is under execution.

$$(P)$$ The processor pushes the process status of $$L$$ onto the control stack.
$$(Q)$$ The processor finishes the execution of the current instruction.
$$(R)$$ The processor executes the interrupt service routine.
$$(S)$$ The processor pops the process status of $$L$$ from the control stack.
$$(T)$$ The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?

A
$$QPTRS$$
B
$$PTRSQ$$
C
$$TRPQS$$
D
$$QTPRS$$
3
GATE CSE 2018
Numerical
+1
-0
A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ chip is $${2^{14}}.$$ The time taken to perform one refresh operation is $$50$$ nanoseconds. The refresh period is $$2$$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
Your input ____
4
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is
A
$$P - N - lo{g_2}K$$
B
$$P - N + lo{g_2}K$$
C
$$P - N - M - W - lo{g_2}\,\,K$$
D
$$P - N - M - W + lo{g_2}\,\,K$$
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