Consider an $$IP$$ packet with a length of $$4,500$$ bytes that includes a $$20$$-byte $$IPv$$$$4$$ header and a $$40$$-byte $$TCP$$ header. The packet is forwarded to an $$IPv4$$ router that supports a Maximum Transmission Unit $$(MTU)$$ of $$600$$ bytes. Assume that the length of the $$IP$$ header in all the outgoing fragments of this packet is $$20$$ bytes. Assume that the fragmentation offset value stored in the first fragment is $$0.$$

The fragmentation offset value stored in the third fragment is _______.

Consider a simple communication system where multiple nodes are connected by a shared broadcast medium (like Ethernet or wireless). The nodes in the system use the following carrier-sense based medium access protocol. A node that receives a packet to transmit will carrier-sense the medium for $$5$$ units of time. If the node does not detect any other transmission in this duration, it starts transmitting its packet in the next time unit. If the node detects another transmission, it waits until this other transmission finishes, and then begins to carrier-sense for $$5$$ time units again. Once they start to transmit, nodes do not perform any collision detection and continue transmission even if a collision occurs. All transmissions last for $$20$$ units of time. Assume that the transmission signal travels at the speed of $$10$$ meters per unit time in the medium.

Assume that the system has two nodes $$P$$ and $$Q,$$ located at a distance $$d$$ meters from each other. $$P$$ starts transmitting a packet at time $$t=0$$ after successfully completing its carrier-sense phase. Node $$Q$$ has a packet to transmit at time $$t=0$$ and begins to carrier-sense the medium.

The maximum distance $$d$$ (in meters, rounded to the closest integer) that allows $$Q$$ to successfully avoid a collision between its proposed transmission and $$P’s$$ ongoing transmission is _____.

Consider the following processor design characteristics.

$$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only
$$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format
$$\,\,\,{\rm I}{\rm I}{\rm I}.\,\,\,\,\,$$ Hardwired control unit

Which of the characteristics above are used in the design of a $$RISC$$ processor?

The following are some events that occur after a device controller issues an interrupt while process $$L$$ is under execution.

$$(P)$$ The processor pushes the process status of $$L$$ onto the control stack.
$$(Q)$$ The processor finishes the execution of the current instruction.
$$(R)$$ The processor executes the interrupt service routine.
$$(S)$$ The processor pops the process status of $$L$$ from the control stack.
$$(T)$$ The processor loads the new PC value based on the interrupt.

Which one of the following is the correct order in which the events above occur?