Consider the following statements regarding the slow start phase of the $$TCP$$ congestion control algorithm. Note that $$cwnd$$ stands for the $$TCP$$ congestion window and $$MSS$$ denotes the Maximum Segment Size.

$$(i)$$ $$\,\,\,\,\,\,\,\,\,\,\,$$ The $$cwnd$$ increases by $$2$$ $$MSS$$ on every successful acknowledgment.
$$(ii)$$ $$\,\,\,\,\,\,\,\,\,$$ The $$cwnd$$ approximately doubles on every successful acknowledgement.
$$(iii)$$ $$\,\,\,\,\,\,\,$$ The $$cwnd$$ increases by $$1$$ $$MSS$$ every round trip time.
$$(iv)$$ $$\,\,\,\,\,\,\,\,\,$$ The $$cwnd$$ approximately doubles every round trip time.

Which one of the following is correct?

A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ chip is $${2^{14}}.$$ The time taken to perform one refresh operation is $$50$$ nanoseconds. The refresh period is $$2$$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.

The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is

The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Writeback $$(WB).$$ The $$IF,$$ $$ID,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for every instruction. Consider a sequence of $$100$$ instructions. In the $$PO$$ stage, $$40$$ instructions take $$3$$ clock cycles each, $$35$$ instructions take $$2$$ clock cycles each, and the remaining $$25$$ instructions take $$1$$ clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ______.