The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is

A processor has $$16$$ integer registers $$\left( {R0,\,\,R1,\,\,..\,\,,\,\,R15} \right)$$) and $$64$$ floating point registers $$(F0, F1,… , F63).$$ It uses a $$2$$-byte instruction format. There are four categories of instructions: Type-$$1,$$ Type-$$2,$$ Type-3, and Type-$$4.$$ Type-$$1$$ category consists of four instructions, each with $$3$$ integer register operands $$(3Rs)$$. Type-$$2$$ category consists of eight instructions, each with $$2$$ floating point register operands $$(2Fs).$$ Type-$$3$$ category consists of fourteen instructions, each with one integer register operand and one floating point register operand $$(1R+1F).$$ Type-$$4$$ category consists of $$N$$ instructions, each with a floating point register operand $$(1F).$$

The maximum value of $$N$$ is __________.

The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Writeback $$(WB).$$ The $$IF,$$ $$ID,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for every instruction. Consider a sequence of $$100$$ instructions. In the $$PO$$ stage, $$40$$ instructions take $$3$$ clock cycles each, $$35$$ instructions take $$2$$ clock cycles each, and the remaining $$25$$ instructions take $$1$$ clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ______.

A queue is implemented using a non-circular singly linked list. The queue has a head pointer and a tail pointer, as shown in the figure. Let $$n$$ denote the number of nodes in the queue. Let $$enqueue$$ be implemented by inserting a new node at the head, and $$dequeue$$ be implemented by deletion of a node from the tail.

Which one of the following is the time complexity of the most time-efficient implementation of $$enqueue$$ and $$dequeue,$$ respectively, for this data structure?