A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ chip is $${2^{14}}.$$ The time taken to perform one refresh operation is $$50$$ nanoseconds. The refresh period is $$2$$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.

A processor has $$16$$ integer registers $$\left( {R0,\,\,R1,\,\,..\,\,,\,\,R15} \right)$$) and $$64$$ floating point registers $$(F0, F1,… , F63).$$ It uses a $$2$$-byte instruction format. There are four categories of instructions: Type-$$1,$$ Type-$$2,$$ Type-3, and Type-$$4.$$ Type-$$1$$ category consists of four instructions, each with $$3$$ integer register operands $$(3Rs)$$. Type-$$2$$ category consists of eight instructions, each with $$2$$ floating point register operands $$(2Fs).$$ Type-$$3$$ category consists of fourteen instructions, each with one integer register operand and one floating point register operand $$(1R+1F).$$ Type-$$4$$ category consists of $$N$$ instructions, each with a floating point register operand $$(1F).$$

The maximum value of $$N$$ is __________.

Consider the following processor design characteristics.

$$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only
$$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format
$$\,\,\,{\rm I}{\rm I}{\rm I}.\,\,\,\,\,$$ Hardwired control unit

Which of the characteristics above are used in the design of a $$RISC$$ processor?

The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is