1
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2, $$ and $$R3.$$ GATE CSE 2004 Computer Organization - Machine Instructions and Addressing Modes Question 21 English

Let the clock cycles required for various operations be as follows:
Register to/from memory transfer:
$$3$$ clock cycles
ADD with both operands in register:
$$1$$ clock cycle
Instruction fetch and decode:
$$2$$ clock cycles per word

The total number of clock cycle required to execute the program is

A
$$29$$
B
$$24$$
C
$$23$$
D
$$20$$
2
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?
A
Neither vectored interrupt nor multiple interrupting devices are possible
B
Vectored interrupts are not possible but multiple interrupting devices are possible
C
Vectored interrupts and multiple interrupting devices are both possible
D
Vectored interrupt is possible but multiple interrupting devices are not possible
3
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
How many $$8$$-bit characters can be transmitted per second over $$9600$$ baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity bit
A
$$600$$
B
$$800$$
C
$$876$$
D
$$1200$$
4
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
A Hard disk with a transfer rate of $$10Mbytes/second$$ is constantly transferring data to memory using $$DMA.$$ The processor runs at $$600MHz$$ and takes $$300$$ and $$900$$ clock cycles to initiate and complete $$DMA$$ transfer respectively. The size of the data transfer is $$20$$ $$KB.$$ What is the $$\% $$ of processor time consumed for this operation ?
A
$$10\% $$
B
$$1\% $$
C
$$0.1\% $$
D
$$0.01\% $$
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