Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2, $$ and $$R3.$$

Let the clock cycles required for various operations be as follows:
Register to/from memory transfer:
$$3$$ clock cycles
ADD with both operands in register:
$$1$$ clock cycle
Instruction fetch and decode:
$$2$$ clock cycles per word

The total number of clock cycle required to execute the program is

Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2, $$ and $$R3.$$

Consider that the memory is byte addressable with word size $$32$$ bits, and the program has been loaded starting from memory location $$1000$$ (decimal). If an interrupt occurs while the $$CPU$$ has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Which of the following addressing modes are suitable for program relocation at run time?
$$1.$$ Absolute addressing
$$2.$$ Based addressing
$$3.$$ Relative addressing
$$4.$$ Indirect addressing

A $$4$$-stage pipeline has the stage delays as $$150, 120,160$$ and $$140$$ nano seconds respectively. Registers that are used between the stages have a delay of $$5$$ nanoseconds each. Assuming constant clocking rate, the total time taken to process $$1000$$ data items on this pipeline will be