Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used $$(LRU)$$ scheme. The number of cache misses for the following sequence of blocks addresses is $$8,12,0,12,8$$

The microinstructions stored in the control memory of a processor have a width of $$26$$ bits. Each microinstruction is divided into three fields: a micro-operation of $$13$$ bits, a next address field $$(X),$$ and a $$MUX$$ select field $$(Y).$$ There are $$8$$ status bits in the inputs of the $$MUX$$.

How many bits are there in the $$X$$ and $$Y$$ fields, and what is the size of the control memory in number of words?

A Hard disk with a transfer rate of $$10Mbytes/second$$ is constantly transferring data to memory using $$DMA.$$ The processor runs at $$600MHz$$ and takes $$300$$ and $$900$$ clock cycles to initiate and complete $$DMA$$ transfer respectively. The size of the data transfer is $$20$$ $$KB.$$ What is the $$\% $$ of processor time consumed for this operation ?

How many $$8$$-bit characters can be transmitted per second over $$9600$$ baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity bit