1
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
What is the result of evaluating the following two expressions using three $$-$$ digit floating point arithmetic with rounding?
$$\eqalign{ & \left( {113. + - 111.} \right) + 7.51 \cr & 113. + \left( { - 111. + 7.51} \right) \cr} $$
A
$$9.51$$ and $$10.0$$ respectively
B
$$10.0$$ and $$9.51$$ respectively
C
$$9.51$$ and $$9.51$$ respectively
D
$$10.0$$ and $$10.0$$ respectively
2
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
$$A$$ $$4$$-bit carry look ahead adder, which adds two $$4$$-bit numbers, is designed using $$AND,$$ $$OR,$$ $$NOT,$$ $$NAND,$$ $$NOR$$ gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level $$AND$$-$$OR$$ logic.
A
$$4$$ times units
B
$$6$$ time units
C
$$10$$ time units
D
$$12$$ time units
3
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used $$(LRU)$$ scheme. The number of cache misses for the following sequence of blocks addresses is $$8,12,0,12,8$$
A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
4
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
A $$4$$-stage pipeline has the stage delays as $$150, 120,160$$ and $$140$$ nano seconds respectively. Registers that are used between the stages have a delay of $$5$$ nanoseconds each. Assuming constant clocking rate, the total time taken to process $$1000$$ data items on this pipeline will be
A
$$120.4$$ microseconds
B
$$160.5$$ microseconds
C
$$165.5$$ microseconds
D
$$590.0$$ microseconds
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