Which of the following addressing modes are suitable for program relocation at run time?
$$1.$$ Absolute addressing
$$2.$$ Based addressing
$$3.$$ Relative addressing
$$4.$$ Indirect addressing

A $$4$$-stage pipeline has the stage delays as $$150, 120,160$$ and $$140$$ nano seconds respectively. Registers that are used between the stages have a delay of $$5$$ nanoseconds each. Assuming constant clocking rate, the total time taken to process $$1000$$ data items on this pipeline will be

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used $$(LRU)$$ scheme. The number of cache misses for the following sequence of blocks addresses is $$8,12,0,12,8$$

Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?