1
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2, $$ and $$R3.$$ GATE CSE 2004 Computer Organization - Machine Instructions and Addressing Modes Question 22 English

Consider that the memory is byte addressable with word size $$32$$ bits, and the program has been loaded starting from memory location $$1000$$ (decimal). If an interrupt occurs while the $$CPU$$ has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

A
$$1007$$
B
$$1020$$
C
$$1024$$
D
$$1028$$
2
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider the following program segment for a hypothetical $$CPU$$ having three user registers $$R1,R2, $$ and $$R3.$$ GATE CSE 2004 Computer Organization - Machine Instructions and Addressing Modes Question 21 English

Let the clock cycles required for various operations be as follows:
Register to/from memory transfer:
$$3$$ clock cycles
ADD with both operands in register:
$$1$$ clock cycle
Instruction fetch and decode:
$$2$$ clock cycles per word

The total number of clock cycle required to execute the program is

A
$$29$$
B
$$24$$
C
$$23$$
D
$$20$$
3
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?
A
Neither vectored interrupt nor multiple interrupting devices are possible
B
Vectored interrupts are not possible but multiple interrupting devices are possible
C
Vectored interrupts and multiple interrupting devices are both possible
D
Vectored interrupt is possible but multiple interrupting devices are not possible
4
GATE CSE 2004
MCQ (Single Correct Answer)
+1
-0.3
How many $$8$$-bit characters can be transmitted per second over $$9600$$ baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity bit
A
$$600$$
B
$$800$$
C
$$876$$
D
$$1200$$
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