1
GATE EE 2017 Set 2
Numerical
+2
-0
Consider the system described by the following state space representation
$$\eqalign{ & \left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet \left( t \right)} \cr {\mathop {{x_2}}\limits^ \bullet \left( t \right)} \cr } } \right] = \left[ {\matrix{ 0 & 1 \cr 0 & { - 2} \cr } } \right]\left[ {\matrix{ {{x_1}\left( t \right)} \cr {{x_2}\left( t \right)} \cr } } \right] + \left[ {\matrix{ 0 \cr 1 \cr } } \right]u\left( t \right) \cr & y\left( t \right) = \left[ {\matrix{ 1 & 0 \cr } } \right]\left[ {\matrix{ {{x_1}\left( t \right)} \cr {{x_2}\left( t \right)} \cr } } \right] \cr} $$
$$\eqalign{ & \left[ {\matrix{ {\mathop {{x_1}}\limits^ \bullet \left( t \right)} \cr {\mathop {{x_2}}\limits^ \bullet \left( t \right)} \cr } } \right] = \left[ {\matrix{ 0 & 1 \cr 0 & { - 2} \cr } } \right]\left[ {\matrix{ {{x_1}\left( t \right)} \cr {{x_2}\left( t \right)} \cr } } \right] + \left[ {\matrix{ 0 \cr 1 \cr } } \right]u\left( t \right) \cr & y\left( t \right) = \left[ {\matrix{ 1 & 0 \cr } } \right]\left[ {\matrix{ {{x_1}\left( t \right)} \cr {{x_2}\left( t \right)} \cr } } \right] \cr} $$
If $$u(t)$$ is a unit step input and $$\left[ {\matrix{ {{x_1}\left( 0 \right)} \cr {{x_2}\left( 0 \right)} \cr } } \right] = \left[ {\matrix{ 1 \cr 0 \cr } } \right],$$ the value of output $$y(t)$$ at $$t=1$$ sec (rounded off to three decimal places) is _____________.
Your input ____
2
GATE EE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
For a $$3$$ -input logic circuit shown below, the output $$Z$$ can be expressed as
![GATE EE 2017 Set 2 Digital Electronics - Boolean Algebra Question 2 English](https://gateclass.static.cdn.examgoal.net/9q8DVVD9ZY9RuYbxe/U3XUHovbSbmWej6hzVG8ljC6iHbvR/kJ8OagvetVUuwoBFdBbxZp/uploadfile.jpg)
3
GATE EE 2017 Set 2
Numerical
+2
-0
For the synchronous sequential circuit shown below, the output $$Z$$ is zero for the initial conditions $${Q_A}{Q_B}{Q_C} = Q{'_A}Q{'_B}Q{'_C} = 100.$$
![GATE EE 2017 Set 2 Digital Electronics - Sequential Circuits Question 8 English](https://gateclass.static.cdn.examgoal.net/2yiHQfSpPowUQ8qyK/OgqwZRxEz0czrNn46IYTwKXfJua0E/56Pxg7rx0smqewIZNRiClQ/uploadfile.jpg)
The minimum number if clock cycles after which the output $$Z$$ would again become zero is _____________.
Your input ____
4
GATE EE 2017 Set 2
MCQ (Single Correct Answer)
+2
-0.6
For the network given in figure below, the Thevenin's voltage Vab is
![GATE EE 2017 Set 2 Electric Circuits - Network Theorems Question 27 English](https://gateclass.cdn.examgoal.net/examside/questions/334b2d611b578beb8e57dbb4b8951b3f561e7f2aa441caa5127c2c092b176023.jpg)
![GATE EE 2017 Set 2 Electric Circuits - Network Theorems Question 27 English](https://gateclass.cdn.examgoal.net/examside/questions/334b2d611b578beb8e57dbb4b8951b3f561e7f2aa441caa5127c2c092b176023.jpg)
Paper analysis
Total Questions
Analog Electronics
2
Control Systems
5
Digital Electronics
2
Electric Circuits
6
Electrical and Electronics Measurement
3
Electrical Machines
9
Electromagnetic Fields
3
Engineering Mathematics
9
Power Electronics
6
Power System Analysis
6
Signals and Systems
3
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