Which of the following logic circuits is a realization of the function $$F$$ whose karnaugh map is shown in figure

A cascade of three identical modulo -$$5$$ counters has an over all modulus of

An output device is interfaced with $$8$$ bit microprocessor $$8085$$$$A.$$ The interfacing circuit is shown in figure

The interfacing circuit makes use of $$3$$ line to $$8$$ line decoder having $$3$$ enable lines $${E_1}\,\,\overline E {}_2,$$ $$\,\overline E {}_3$$. The address of the device is

C₀ is the capacitance of a parallel plate capacitor with air as dielectric (as in figure (a)). If, half of the entire gap as shown in figure (b) is filled with a dielectric of permittivity $$\in_r$$ , the expression for the modified capacitance is