1
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively
A
$$10, 17$$
B
$$10,22$$
C
$$15,17$$
D
$$5, 17$$
2
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
A $$5$$ stage pipelined $$CPU$$ has the following sequence of stages $$IF$$-Instruction fetch from instruction memory, $$RD$$-Instruction decode and register read, $$EX$$-Execute: $$ALU$$ operation for data and address computation, $$MA$$-Data memory access-for write access the register read and $$RD$$ stage it used, $$WB$$-Register write back.

Consider the following sequence of instructions:
$$\eqalign{ & {{\rm I}_1}:L\,R0,\,\,Loc1;\,R0 < \,\, = M\,[Loc1] \cr & {{\rm I}_2}:A\,R0,\,R0;\,\,\,\,\,\,R0 < \,\, = R0 + R0 \cr & {{\rm I}_3}:A\,R2,\,R0;\,\,\,\,\,\,R2 < \,\, = R2 - R0 \cr} $$

Let each stage takes one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $${{\rm I}_1}?$$

A
$$8$$
B
$$10$$
C
$$12$$
D
$$15$$
3
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider a three word machine instruction $$ADD$$ $$A$$ $$\left[ {{R_0}} \right],\,@\,B$$

The first operand (destination) ''$$A$$ $$\left[ {{R_0}} \right]''$$ uses indexed addressing mode with $${{R_0}}$$ as the index register. The second operand (source) $$''@B''$$ used indirect addressing mode. $$A$$ and $$B$$ are memory addresses residing at the second and the third words, respectively. The first word of the instruction specific the opcode, the index register designation and the source and destination addressing modes. During execution of $$ADD$$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

A
$$3$$
B
$$4$$
C
$$5$$
D
$$6$$
4
GATE CSE 2005
MCQ (Single Correct Answer)
+1
-0.3
Normally user programs are prevented from handling $${\rm I}/O$$ directly by $${\rm I}/O$$ instructions in them. For $$CPUs$$ having explicit $${\rm I}/O$$ instructions, such $${\rm I}/O$$ protection is ensured by having the $${\rm I}/O$$ instructions privileged. In a $$CPU$$ with memory mapped $${\rm I}/O$$, there is no explicit $${\rm I}/O$$ instruction. Which one of the following is true for a $$CPU$$ with memory mapped $${\rm I}/O$$ ?
A
$${\rm I}/O$$ protection is ensured by operating system routine(s)
B
$${\rm I}/O$$ protection is ensured by a hardware trap
C
$${\rm I}/O$$ protection is ensured during system configuration
D
$${\rm I}/O$$ protection is not possible
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
CBSE
Class 12