The data given below. Solve the problems and choose the correct answer.

The normalized representation for the above format is specified as follows. The mantissa has an implicit preceding the binary (radix) point. Assume that only $$0's$$ are padded in while shifting a field. The normalized representation of the above $$\left( {0.239 \times {2^{13}}} \right)$$ is

Increasing the $$RAM$$ of a computer typically improves performance because

Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

A $$5$$ stage pipelined $$CPU$$ has the following sequence of stages $$IF$$-Instruction fetch from instruction memory, $$RD$$-Instruction decode and register read, $$EX$$-Execute: $$ALU$$ operation for data and address computation, $$MA$$-Data memory access-for write access the register read and $$RD$$ stage it used, $$WB$$-Register write back.

Consider the following sequence of instructions:
$$\eqalign{ & {{\rm I}_1}:L\,R0,\,\,Loc1;\,R0 < \,\, = M\,[Loc1] \cr & {{\rm I}_2}:A\,R0,\,R0;\,\,\,\,\,\,R0 < \,\, = R0 + R0 \cr & {{\rm I}_3}:A\,R2,\,R0;\,\,\,\,\,\,R2 < \,\, = R2 - R0 \cr} $$

Let each stage takes one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $${{\rm I}_1}?$$