Increasing the $$RAM$$ of a computer typically improves performance because

Consider a three word machine instruction $$ADD$$ $$A$$ $$\left[ {{R_0}} \right],\,@\,B$$

The first operand (destination) ''$$A$$ $$\left[ {{R_0}} \right]''$$ uses indexed addressing mode with $${{R_0}}$$ as the index register. The second operand (source) $$''@B''$$ used indirect addressing mode. $$A$$ and $$B$$ are memory addresses residing at the second and the third words, respectively. The first word of the instruction specific the opcode, the index register designation and the source and destination addressing modes. During execution of $$ADD$$ instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

A $$5$$ stage pipelined $$CPU$$ has the following sequence of stages $$IF$$-Instruction fetch from instruction memory, $$RD$$-Instruction decode and register read, $$EX$$-Execute: $$ALU$$ operation for data and address computation, $$MA$$-Data memory access-for write access the register read and $$RD$$ stage it used, $$WB$$-Register write back.

Consider the following sequence of instructions:
$$\eqalign{ & {{\rm I}_1}:L\,R0,\,\,Loc1;\,R0 < \,\, = M\,[Loc1] \cr & {{\rm I}_2}:A\,R0,\,R0;\,\,\,\,\,\,R0 < \,\, = R0 + R0 \cr & {{\rm I}_3}:A\,R2,\,R0;\,\,\,\,\,\,R2 < \,\, = R2 - R0 \cr} $$

Let each stage takes one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $${{\rm I}_1}?$$

Consider the following data path of a $$CPU$$

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''add$$ $$R0$$, $$R1''$$ has the register transfer interpretation $$R0 < = R0 + R1.$$ The minimum number of cycles needed for execution cycle of this instruction is