A $$5$$ stage pipelined $$CPU$$ has the following sequence of stages $$IF$$-Instruction fetch from instruction memory, $$RD$$-Instruction decode and register read, $$EX$$-Execute: $$ALU$$ operation for data and address computation, $$MA$$-Data memory access-for write access the register read and $$RD$$ stage it used, $$WB$$-Register write back.

Consider the following sequence of instructions:
$$\eqalign{ & {{\rm I}_1}:L\,R0,\,\,Loc1;\,R0 < \,\, = M\,[Loc1] \cr & {{\rm I}_2}:A\,R0,\,R0;\,\,\,\,\,\,R0 < \,\, = R0 + R0 \cr & {{\rm I}_3}:A\,R2,\,R0;\,\,\,\,\,\,R2 < \,\, = R2 - R0 \cr} $$

Let each stage takes one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $${{\rm I}_1}?$$

Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

Increasing the $$RAM$$ of a computer typically improves performance because

Consider the following data path of a $$CPU$$

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''call$$ $$Rn,sub''$$ is a two word instruction. Assuming that $$PC$$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is $$$\eqalign{ & Rn < = PC + 1; \cr & PC < = M\left[ {PC} \right]; \cr} $$$
The minimum number of $$CPU$$ clock cycles needed during the execution cycle of this instruction is :