The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$
The instruction $$''call$$ $$Rn,sub''$$ is a two word instruction. Assuming that $$PC$$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is
$$$\eqalign{
& Rn < = PC + 1; \cr
& PC < = M\left[ {PC} \right]; \cr} $$$
The minimum number of $$CPU$$ clock cycles needed during the execution cycle of this instruction is :
The normalized representation for the above format is specified as follows. The mantissa has an implicit preceding the binary (radix) point. Assume that only $$0's$$ are padded in while shifting a field. The normalized representation of the above $$\left( {0.239 \times {2^{13}}} \right)$$ is
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