Normally user programs are prevented from handling $${\rm I}/O$$ directly by $${\rm I}/O$$ instructions in them. For $$CPUs$$ having explicit $${\rm I}/O$$ instructions, such $${\rm I}/O$$ protection is ensured by having the $${\rm I}/O$$ instructions privileged. In a $$CPU$$ with memory mapped $${\rm I}/O$$, there is no explicit $${\rm I}/O$$ instruction. Which one of the following is true for a $$CPU$$ with memory mapped $${\rm I}/O$$ ?

A device with data transfer rate $$10$$ $$KB/sec$$ is connected to a $$CPU.$$ Data is transferred byte-wise. Let the interrupt overhead be $$4$$ $$\mu \sec $$. The byte transfer time between the device interface register and $$CPU$$ or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlIed mode?

Consider the disk drive with the following specifications $$16$$ surfaces, $$512$$ tracks/surface, $$512$$ sectors/track, $$1$$ $$KB/sector$$, rotation speed $$3000$$ $$rpm.$$ The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a $$4$$ byte word from the memory in each $$DMA$$ cycle. Memory cycle time is $$40$$ $$nsec$$. The maximum percentage of time that the $$CPU$$ gets blocked during $$DMA$$ operation is

Consider the following data path of a $$CPU$$

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''add$$ $$R0$$, $$R1''$$ has the register transfer interpretation $$R0 < = R0 + R1.$$ The minimum number of cycles needed for execution cycle of this instruction is