1
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
Suppose we want to synchronize two concurrent processes P and Q using binary semaphores S and T. The code for the processes P and Q is shown below.

Process P:

while(1){
  W:
  Print '0';
  Print '0';
  X:
}

Process Q:

while(1){
  Y:
  Print '1';
  Print '1';
  Z:
}
Synchronization statements can be inserted only at points W, X, Y, and Z.

Which of the following will ensure that the output string never contains a substring of the form 01n0 or 10n1 where n is odd?

A
P(S) at W, V(S) at X, P(T) at Y, V(T) at Z, S and T initially 1
B
P(S) at W, V(T) at X, P(T) at Y, V(S) at Z, S and T initially 1
C
P(S) at W, V(S) at X, P(S) at Y, V(S) at Z, S initially 1
D
V(S) at W, V(T) at X, P(S) at Y, P(T) at Z, S and T initially 1
2
GATE CSE 2003
MCQ (Single Correct Answer)
+1
-0.3
In a system with $$32$$ bit virtual addresses and $$1$$ $$KB$$ page size, use of one-level page tables for virtual to physical address translation is not practical because of
A
The large amount of internal fragmentation
B
The large amount of external fragmentation
C
The large memory overhead in maintaining page tables.
D
The large computation overhead in the translation process
3
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
Which of the following is NOT an advantage of using shared, dynamically linked libraries as opposed to using statically linked libraries?
A
Smaller sizes of executable files
B
Lesser overall page fault rate in the system
C
Faster program startup
D
Existing programs need not be re-linked to take advantage of newer versions of libraries.
4
GATE CSE 2003
MCQ (Single Correct Answer)
+2
-0.6
A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $$10$$ most significant bits of the virtual address are used as index into the first level page table while the next $$10$$ bits are used as index into the second level page table. The $$12$$ least significant bits of the virtual address are used as offset within thepage. Assume that the page table entries in both levels of page tables are $$4$$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $$96$$%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $$90$$%. Main memory access time is $$10$$ ns, cache access time is $$1$$ ns, and TLB access time is also $$1$$ ns.

Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest $$0.5$$ ns)

A
$$1.5$$ ns
B
$$2$$ ns
C
$$3$$ ns
D
$$4$$ ns
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